The present invention is directed in general toward frequency-locked loops and, more particularly, toward a digital frequency locked loop implemented with programmable signal processing methods for use in systems employing staggered sampling.
There are many devices and methods available at the moment for determining frequency and for locking to an analog signal. Generally, they fall into two broad classes, to wit, analog and digital. Although analog frequency-locked loops once dominated the art, continued progress in semiconductor technology, enhancing the performance, speed, and reliability of integrated circuits while simultaneously reducing their size and cost, has resulted in strong interest in the implementation of the frequency-locked loop in the digital domain.
Aside from the obvious size and cost advantages associated with digital systems, a digital version of the frequency locked loop alleviates many other problems associated with its analog counterpart, namely: sensitivity to dc drifts and component saturations, difficulties encountered in building higher order loops, and the need for initial calibration and periodic adjustments. In addition, since many systems requiring frequency locking already employ digital signal processing devices to perform other functions, a digital frequency locked loop can make use of these processing devices eliminating the need for other specialized circuitry and further reducing circuit cost.
Notwithstanding the increasing desirability of a digital version of the frequency locked loop, existing implementations have proven inadequate for most applications. This is in large measure because conventional digital devices for locking a local signal to an analog input signal determine the frequency of the input signal by measuring the time interval between zero crossings. However, this method of measuring the input frequency is sensitive to noise which may cause the timing of the zero crossing to fluctuate and, therefore, these devices are inadequate for frequency locking. Further, this method is costly to implement because a dedicated counter is necessary to perform the zero crossing measurement. Alternatively, a digital processor may be used for this measurement, however, the processor performing the frequency measurement must either be dedicated to the measurement or must be interrupted in the performance of other tasks to measure the zero crossing time.
Further, other methods for determining the frequency of an analog input can not be adapted to systems employing staggered sampling of the input signal. This is mainly due to the effects of frequency drift between samples. Nonetheless, in many systems which perform digital processing of input signals staggered sampling is desirable. These systems further require frequency locking to maintain the integrity of the samples. Hence, a digital frequency locked loop which can be implemented using programmable processing techniques and which makes use of staggered samples can be implemented in these systems with no need for additional circuitry and thus at reduced production cost.
There exists, therefore, a need to determine the frequency of an analog signal with a high degree of accuracy and to use this information to improve both the performance and productivity of processing elements used in digital frequency locked loops. Further, there exists the need for a frequency locked loop which performs the frequency deviation calculation using staggered samples as its input.